효율적인 위성/지상 전송을 위한 저전력 고속 LDPC 복호 알고리즘 및 FPGA 구현에 관한 연구

Abstract

Efficient support for digital video broadcasting (DVB) services in mobile systems is crucial issue for mobile operators and broadcasters. Currently several DVB systems have been developed internationally, to meet the requirements of broadcasters. The representative standards are DVB-SSP and DVB-S2 specifications for mobile and broadband multimedia services by using hybrid satellite and terrestrial transmission schemes. The standards for satellite and terrestrial transmission such as DVB-S2 and DVB-T2 use the Low Density Parity Check(LDPC) code to correct transmission errors.

In a long-term fading environment, the MPE-FEC(Multi-Protocol Encapsulation-Forward Error Correction) scheme which adopts the erasure Reed Solomon (e-RS) code and the virtual interleaver is used to compensate the fading effects.

The e-RS can correct more erroneous code symbols than the conventional non-erasure Reed Solomon code, which is one of the advantages of e-RS code. The erasure information can be obtained from CRC error detection. However, a critical factor must be considered for dealing with a long-term fading channel. In fact, at the end of every MPE-FEC section, there is a CRC-32 field calculated over the entire section, to detect erroneous sections at the receiver side. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. This implies that if there is one real byte error in a IP packet of 512 bytes, 511 correct bytes should be erased from the frame. This causes performance degradation in erasure RS decoding scheme.

This paper has proposed new efficient decoding algorithms for MPE-FEC code and the DVB-S2 LDPC code. A new MPE-FEC decoding algorithm based on LLR infomation has been proposed to increase the decoding performance. This paper proposed a new MPE-FEC decoding algorithm based on LLR. If the number of erased bytes is less than the error correction capability, an erasure RS code is used, otherwise, a non-erasure decoder that buffered another received symbol memory is used. The main difference between the decoding methods based on CRC and LLR analyzed in this paper in terms of performance, is the manner in which the erasure information is obtained and it is utilized.

In the study of LDPC decoding algorithm, two kinds of LDPC decoding algorithm have been studied to reduce the computational complexity and decoding speed. There are two kinds of low computational complexity algorithms such as early edge detection algorithm and early stop algorithm. Also, in the high-speed LDPC decoding algorithms, Horizontal Shuffle Scheduling(HSS) and Vertical Shuffle Scheduling(VSS) algorithm can be used. In case of CNU methods,SP (Sum Product) method is often used in LDPC decoding. However SP needs LUT (Look UP Table) that is critical path in LDPC decoding speed [4]. In this paper, a new SC-NMS method is proposed. The SC-NMS method needs only normalized scaling factor instead of LUT, which reduces the complexity of computation for SP approximation. As a result, the number of iteration can be reduced to the half of the conventional algorithm, algorithm with the same performance of the SP algorithm.

Finally, in this paper, the hardware structure of high-speed LDPC decoder impelementation has been proposed and its throughtput has been also investigated. The LDPC decoder has been implemented based on HSS algorithm by using FPGA chip xc5vlx155t model. A new memory structure and data permutation method has been proposed and verified by real hardware experiment. This new structure has been compared with conventional structure in the point of decoding speed. According to the result, the decoding throughput of the proposed structure based on SC-NMS algorithm has been improved by 40%.